The invention generally relates to the field of semiconductor device manufacture and more particularly to a new method of making V-MOS field effect transistors.
The basic advantage of V-MOS technology is the ability to provide a very short channel, L, between the source and drain regions of a field effect transistor without any deleterious effects. Prior art methods of manufacturing V-MOS field effect transistors rely on the fact that anisotropic etchs are available that etch certain silicon crystal planes more readily than other crystal planes. N.sub.2 H.sub.4 and KOH are two such etchants that dissolve the &lt;100&gt; planes much more rapidly than the &lt;111&gt; planes. The channel length, L, of the V-MOS transistor can be easily calculated. &lt;111&gt; planes intersect the &lt;100&gt; planes at 55 degrees. Knowing this, the channel length, L, is given by the following equation: EQU L=2(0.86W-1.2X.sub.j),
where W is the mask opening and X.sub.j is the diffusion depth. The channel length, L, is then controlled by the mask opening, W, and the diffusion depth, X.sub.j, both of which can be only moderately controlled at best. Because of this, diffusion spikes which short the source and drain regions of the transistor sometimes occur. A vast improvement in channel length control could be achieved if it were possible to eliminate the effect of either of the parameters W or X.sub.j.